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SigmanticAI

The Cursor for Chip Design - Delivering Silicon-Ready Chip Designs…

SigmanticAI is building an AI-native hardware development assistant that automates the entire RTL design flow, from natural language to synthesizable HDL and testbenches, inside a seamless VSCode fork. Powered by fine-tuned Verilog LLMs, reinforcement learning, and real compiler feedback, SigmanticAI iteratively refines code until it compiles and passes synthesis, no matter how complex the design. It’s like the Cursor for HDL design. In addition to code generation, SigmanticAI can generate token-level annotations and onboarding documents to accelerate ramp-up for new engineers. With support for both cloud and on-prem deployment, it integrates with existing EDA tools to dramatically reduce debug time, improve collaboration, and accelerate hardware design across teams
Active Founders
Rohil Khare
Rohil Khare
Founder
I’m Rohil Khare, Co-Founder of SigmanticAI. I studied EECS at UC Berkeley and previously worked at Amazon. In high school, I filed provisional patents in IoT as an early innovator, and since then I’ve worked at multiple startups at the intersection of hardware and machine learning. At Berkeley, I conducted research at BAIR and the Architecture Group, and published at ICRA. Now, at SigmanticAI, I’m building AI-native tooling that accelerates the creation of custom chip designs and silicon.
Tamzid Razzaque
Tamzid Razzaque
Founder
I'm Tamzid Razzaque, Co-Founder of SigmanticAI. I studied EECS at UC Berkeley, with a focus on integrating AI applications with custom hardware design. I am continuing this passion at YC. I previously worked at Apple on custom circuits and researched at BWRC and BETR on custom FPGA accelerators.
Company Launches
SigmanticAI - The Cursor for Hardware Design
See original launch post

Hey YC! We're Tamzid and Rohil from SigmanticAI.

The Problem with Creating Custom Hardware

  • HDL tooling hasn’t changed much since the '90s: still slow, manual, and fragmented
  • Debugging eats up majority of hardware dev time
  • There's no seamless AI-native experience for building and reasoning about HDL

Our Solution

SigmanticAI. What it can do:

  • Natural language to synthesizable Verilog + testbenches
  • RL-driven debugging loop
  • Built-in onboarding, codebase annotation, and spec documentation generation
  • LLM-powered on both cloud and fully air-gapped/on-prem deployments
  • Seameless integration with VScode + your existing synthesis tools from Cadence, Synopsys, etc.

We’ve already made a RISCV CPU start to finish with it, onboarded our first paying customer, and are getting 90%+ accuracy on the VerilogEval benchmark (NVIDIA framework)


Demo video
https://youtu.be/Cq3hpMflIA8


Asks!

  • We want to talk to:
    • Anyone working with FPGAs, custom chips, ML accelerators, or RISC-V cores
    • Anyone working in EDA
    • Anyone working with fine tuned LLMs for hardware
  • Try us out! Thank you!

Who We Are

We’ve spent years working on both LLMs and hardware. After working at Apple (Tamzid) and Amazon (Rohil) and research in FPGA mapping and LLaMA fine-tuning, we realized the real bottleneck in hardware design is tooling. We’ve built custom CPUs, worked with EDA stacks, and experienced the pain firsthand. Conversations with engineers at Northrop Grumman, SciEngines, and Quadric made it clear: hardware desperately needs a smarter workflow.

YC Photos
SigmanticAI
Founded:2025
Batch:Summer 2025
Team Size:2
Status:
Active
Location:Dublin, CA
Primary Partner:Diana Hu